Over the years improvements in the design and operation of signal processing components, such as digital bipolar logic circuits, have provided increased speed and reduced power consumption. From the early days of DTL and T.sup.2 L devices, bipolar logic has expanded to include ECL, I.sup.2 L, ISL and STL circuits. Because these newer types of logic operate with smaller voltage swings (typically in the 200 mv to 800 mv range, as contrasted with the 1.5 v to 2.0 v swings for older DTL and T.sup.2 L circuits) the time required to charge and discharge the inherent (parasitic) capacitance of the logic gate interconnect links (metalization tracks) is reduced and, consequently, there is obtained an increase in operating speed.
More particularly, associated with each conductor which interconnects logic circuit devices that are contained within an integrated circuit is an inherent parasitic capacitance which must be charged and discharged in the course of switching from one logic state to another. The time T required to produce the voltage swing between the two charge states of the parasitic capacitance of the gate interconnect can be expressed as T=CV/I, where C is the parasitic capacitance of the gate interconnection link, V is the voltage swing on the link, and I is the current flow.
From this relationship it can be seen that reductions in voltage swing on the interconnects increase the speed of operation of the logic. However, the degree to which the logic circuit is capable of reducing these voltage swings depends upon trade offs in noise margin and internal ground line drops.